With increasing speeds for moving data around a system, the problems associated with system test or debug increases. For system debug, key commands going to a memory device such as a dynamic random access memory (DRAM), for example, need to be identified. This identification is made to determine if the correct command was received by the DRAM. Further, once this identification is made, a test instrument such as an oscilloscope can be used to capture other signals.
System test and debug is becoming increasingly difficult due to complexities associated with accessing all signals on packages such as fine-pitch ball grid array (FBGA) packages, since a signal can be on an internal layer and a contact via can be under a chip component. Additionally, adding a probe in the middle of a trace on a chip can cause extra loading creating system fails or system marginality changes. Also increasing speeds used on system buses adds to the complexity of system debug. For DRAMs such as double data rate (DDR) DRAMs, the speed on the command address bus is in the range of up to 400 megahertz going towards 800 megahertz. At these speeds with the application of a test probe to the chip, impedance is altered basically causing signal integrity issues and concerns.